1. Field of the Invention
The present invention relates to a digital filtering circuit (filter) and, more particularly, to a cyclic (or recursive) digital filter suitable for high-speed signal processing.
2. Description of the Prior Art
The general transfer function H(z) for cyclic digital filters is expressed by Equation (1): ##EQU1## where, N is greater than M. Suitably developing the transfer function H(z) allows various types of cyclic digital filter to be constructed. The cyclic digital filters generally fall into three types: direct cyclic digital filter, parallel cyclic digital filter, and cascade cyclic digital filter.
FIGS. 8 and 9 show the theoretical structures of topical direct cyclic digital filters. FIG. 8 illustrates a direct cyclic digital filter in effect when N is greater than M. For this filter, the transfer function H(z) addressing an output signal y.sub.n with respect to an input signal x.sub.n is duly expressed by Equation (1).
In FIG. 8, an encircled plus (+) sign stands for an adder that performs add or add-subtract operations, a triangle for a coefficient multiplier that multiplies an input signal by a coefficient, and a rectangle for a unit time delay circuit that provides a unit-time delay. The symbol x.sub.n represents an input signal, and the symbol Y.sub.n, an output signal. The unit delay time of the unit time delay circuit generally corresponds to one clock pulse.
FIG. 9 depicts the theoretical structure of a direct cyclic digital filter i.e. effect when N is equal to M. The transfer function H(z) in effect at this time is also expressed by Equation (1).
In FIG. 9, as in FIG. 8, an encircled plus (+) sign stands for an adder, a triangle for a coefficient multiplier, and a rectangle for a unit time delay circuit. The symbol x.sub.n represents an input signal, and the symbol an output signal.
FIG. 10 shows the theoretical structure of a typical parallel cyclic digital filter. In FIG. 10, as in FIG. an encircled plus (+) sign stands for an adder, a triangle for a coefficient multiplier, and a rectangle for a unit time delay circuit. The symbol x.sub.n represents an input signal, and the symbol Y.sub.n, an output signal. If N equals M, the transfer function H(z) for this filter is expressed by Equation (2): ##EQU2##
FIG. 11 illustrates the theoretical structure of a typical cascade cyclic digital filter. In FIG. 11, as in FIG. 8, an encircled plus (+) sign stands for an adder, a triangle for a coefficient multiplier, and a rectangle for a unit time delay circuit. The symbol x.sub.n represents an input signal, and the symbol Y.sub.n, an output signal. The transfer function for this filter is expressed by Equation (3): ##EQU3##
For the direct cyclic digital filter whose theoretical structure is shown in FIG. 8, assume that T1 stands for the time required to multiply the filter coefficient, and T2 for the time required For two-input, one-output addition and subtraction. In that case, the practical circuit for high-speed operation may be constructed as shown in FIG. 12.
The cyclic digital filter of FIG. 12 is a direct cyclic digital filter comprising a feed-forward circuit 300 and a feedback loop circuit 320 connected in series.
The feed-forward circuit 300 contains a first feed-forward circuit, a second feed-forward circuit, a third feed-forward circuit, . . . , an M-th feed-forward circuit, and an (M+1)th feed-forward circuit. The first feed-forward circuit comprises a coefficient multiplier 301 that multiplies the input signal x.sub.n by a filter coefficient a.sub.0 ; a unit time delay circuit 302 that delays the result of the multiplication by one clock pulse; and an adder 303 that adds the delayed output from the unit time delay circuit 302 and the delayed output from a lower-stage unit time delay circuit 307 (to be described later). The second feed-forward circuit comprises a coefficient multiplier 304 that multiplies the input signal x.sub.n by a filter coefficient a.sub.1 ; a unit time delay circuit 305 that delays the result of the multiplication by one clock pulse; and an adder 30 that adds the delayed output from the unit time delay circuit 305 and the delayed output from a lower-stage unit time delay circuit 311 (to be described later). The third feed-forward circuit comprises a coefficient multiplier 308 that multiplies the input signal x.sub.n by a filter coefficient a.sub.2 ; a unit time delay circuit 309 that delays the result of the multiplication by one clock pulse; and the adder 310 that adds the delayed output from the unit time delay circuit 309 and the delayed output from a lower-stage unit time delay circuit, not shown. The M-th feed-forward circuit includes a coefficient multiplier 312 that multiplies the input signal x.sub.n by a filter coefficient a.sub.M-1 ; a unit time delay circuit 313 that delays the result of the multiplication by one clock pulse; and an adder 314 that adds the delayed output from the unit time delay circuit 313 and the delayed output from a lower-stage unit time delay circuit 318 (to be described later). The (M+1)th feed-forward circuit contains a coefficient multiplier 316 that multiplies the input signal x.sub.n by a filter coefficient a.sub.M ; a unit time delay circuit 317 that delays the result of the multiplication by one clock pulse; and the unit time delay circuit 318 that delays by one clock pulse the delayed output from the unit time delay circuit 317.
In their feed-forward operations, the first through the (M+1)th feed-forward circuits carry out in parallel the multiplications of the input signal x.sub.n by their respective coefficients and the delaying of the result of such multiplications.
In the feed-forward circuit 300, the unit time delay circuit 307 is located on the output side of the adder 306; the unit time delay circuit 311, on the output side of the adder 310; . . . , and a unit time delay circuit 315, on the output side of the adder 314. The delayed outputs from these unit time delay circuits are supplied, in cascade fashion, to the adders 303, 306, . . . , 314 respectively located lower-stage. This circuit arrangement is intended to prevent individual multiplication time periods, unit delay time periods and addition time periods from getting accumulated.
The feedback loop circuit 320 comprises a unit time delay circuit 321, an adder 322 and another unit time delay circuit 323. The unit time delay circuit 321 latches and delays for a unit time the output coming from the adder 303 in the feed-forward circuit 300. The adder 322 subtracts the result of the addition by an adder 325, to be discussed later, from the delayed output of the unit time delay circuit 321, the result of the subtraction being output as the output signal y.sub.n. The unit time delay circuit 323 latches and delays for a unit time the output from the adder 322.
The feedback loop circuit 320 further comprises a first feedback loop circuit, a second feedback loop circuit, a third feedback loop circuit, . . . , an N-th feedback loop circuit, and an (N+1)th feedback loop circuit. The first feedback loop circuit contains a coefficient multiplier 324 that multiplies the delayed output from the unit time delay circuit 323 by a coefficient b.sub.1 ; an adder 325 that adds the output from the multiplier 324 and the delayed output from a lower-stage unit time delay circuit 328 (to be described later). The second feedback loop circuit has the coefficient multiplier 326 that multiplies the delayed output from the unit time delay circuit 323 by a coefficient b.sub.2 ; and an adder 327 that adds the output from the multiplier 326 and the delayed output from a lower-stage unit time delay circuit 331 (to be described later). The third feedback loop circuit includes a coefficient multiplier 329 that multiplies the delayed output from the unit time delay circuit 323 by a coefficient b.sub.3 ; and an adder 330 that adds the output from the multiplier 329 and the delayed output from a lower-stage unit time delay circuit, not shown. The N-th feedback loop circuit comprises a coefficient multiplier 332 that multiplies the delayed output from the unit time delay circuit 323 by a coefficient b.sub.N-1 ; and an adder 333 that adds the output from the multiplier and the delayed output from a lower-stage unit time delay circuit 336. The (N+1)th feedback loop circuit has a coefficient multiplier 335 that multiplies the delayed output from the unit time delay circuit 323 by a coefficient b.sub.N ; and a unit time delay circuit 336 that delays the output from the multiplier 332 by a unit time.
In addition, the feedback loop circuit 320 has a unit time delay circuit 328 located on the output side of the adder 327, the circuit 328 latching and delaying for a unit time the result of the addition by the adder 327, the delayed output being sent to the adder 325. A unit time delay circuit 331 is located on the output side of the lower-stage adder 330. The delayed output from the unit time delay circuit 331 is fed to the upstream adder 327. Likewise, the output from the unit time delay circuit 336 is supplied to the adder 333.
FIG. 13 illustrates the construction of a simplified version of the direct cyclic digital filter in FIG. 12, the filter of FIG. 13 being constructed by assuming that M=N=1.
The digital filter of FIG. 13 comprises a unit time delay circuit 341 that delays the input signal x.sub.n by a unit time; an adder 342 that subtracts from the delayed output of the unit time delay circuit 341 the result of the multiplication performed by a coefficient multiplier 346 (to be described later); a unit time delay circuit 340 that delays for a unit time the result of the addition by the adder 342; the coefficient multiplier 346 that multiplies the delayed output from the unit time delay circuit 340 by the coefficient b.sub.1 ; a coefficient multiplier 348 that multiplies by the coefficient a.sub.0 the result of the addition by the adder 342; an adder 343 that adds the result of the multiplication by the coefficient multiplier 348 and the result of the multiplication by a coefficient multiplier 349 (to be described later); a coefficient multiplier 349 that multiplies the delayed output from the unit time delay circuit 345 by the coefficient a and a unit time delay circuit 347 that delays for a unit time the result of the addition by the adder 343, the delayed output being output as the output signal y.sub.n. These components of the digital filter in FIG. 13 are interconnected as illustrated.
The practical circuits of the parallel cyclic digital filter and cascade cyclic digital filter are similarly constructed but not shown.
A brief description is made of the operation time (i.e., delay time) of the direct cyclic digital filter by use of the latter's simplified form in FIG. 13. As with the setup of FIG. 12, assume that T1 is the time required by the adder 342 for addition and subtraction and that T2 is the time require by the coefficient multiplier 346 for coefficient multiplication. In that case, the delay time TD in the feedback loop is given as EQU TD=2.times.T1+T2
The delay time TD determines the maximum operation frequency of the cyclic digital filter.
For example, suppose that the cyclic digital filter is utilized in the emphasis or de-emphasis circuit of a high definition VTR (video tape recorder) and that the clock frequency is 44.55 MHz. Here, the delay time of the unit time delay circuit 345 equals the clock time, while the delay time TD exceeds the delay time of the unit time delay circuit 345. For this reason, the direct cyclic digital filter shown in FIG. 12 or FIG. 13 cannot be employed in applications where such high frequencies are involved. The same problem persists with both the parallel cyclic digital filter and the cascade cyclic digital filter.